Alif Semiconductor /AE302F80F55D5AE_CM55_HP_View /USB /GUCTL

Device timeout fine tuning. This bit field is a Host mode parameter which determines how long the host waits for a response from device before considering a timeout. For the DTFT field to take effect, the DTCT bit filed must be set to 0x0. The DTCT value is the number of 60 MHz clocks x 256 to count before considering a device timeout. The minimum value of DTFT is 0x2. Note: When the system latency is larger than the programmed DTCT/DTFT value, if the HC is not able to accept certain transactions on the bus (because of system bus delays), the controller may not release header credits which in turn can cause the host to report a transaction error. Therefore, program this value to be larger than your system delay.

Device timeout coarse tuning. This field is a Host mode parameter which determines how long the host waits for a response from device before considering a timeout. The controller first checks the DTCT value. If it is 0x0, then the timeout value is defined by the DTFT. If it is non-zero, then it uses the following timeout values: Note: When the system latency is larger than the programmed DTCT/DTFT value, if the HC is not able to accept certain transactions on the bus (because of system bus delays), the controller may not release header credits which in turn can cause the host to report a transaction error. Therefore, program this value to be larger than your system delay.

0 (Val_0x0): 0 us-use DTFT value instead

1 (Val_0x1): 500 us

2 (Val_0x2): 1.5 ms

3 (Val_0x3): 6.5 ms

Insert extra delay between FS Bulk OUT transactions. Some FS devices are slow to receive Bulk OUT data and can get stuck when there are consecutive Bulk OUT transactions with short inter-transaction delays. This bit is used to control whether the host inserts extra delay between consecutive Bulk OUT transactions to a FS Endpoint. Note: Setting this bit to 0x1 reduces the Bulk OUT transfer performance for most of the FS devices.

0 (Val_0x0): Host does not insert extra delay between consecutive Bulk OUT transactions to a FS Endpoint.

1 (Val_0x1): Host inserts about 12 us extra delay between consecutive Bulk OUT transactions to a FS Endpoint to work around the device issue.

External extended capability support enable. When set, this bit enables extended capabilities to be implemented outside the controller.

Host IN auto retry. When set, this bit enables the Auto Retry feature. For IN transfers (non-isochronous) that encounter data packets with CRC errors or internal overrun scenarios, the Auto Retry feature causes the HC to reply to the device with a non-terminating retry ACK (that is, an ACK transaction packet with Retry = 1 and NumP != 0). If the Auto Retry feature is disabled (default), the controller responds with a terminating retry ACK (that is, an ACK transaction packet with Retry = 1 and NumP = 0). Note: When enabling Auto Retry feature, if the system latency is large enough to cause the internal PSQ full (PSQ can be full as the result of messages not being processed because of pending fetches before flushing the TxQ due to NRDY/ERDY conditions), then the HC can generate a transaction error.

0 (Val_0x0): Auto Retry is disabled.

1 (Val_0x1): Auto Retry is enabled.

Reserving 85% bandwidth for HS periodic EPs. By default, HC reserves 80% of the bandwidth for periodic EPs. If this bit is set, the bandwidth is relaxed to 85% to accommodate two High-Speed, High-Bandwidth ISOC EPs. USB 2.0 requires 80% bandwidth allocated for ISOC traffic. If two High-Bandwidth ISOC devices (HD webcams) are connected, and if each requires 1024 bytes x 3 packets per Micro-Frame, then the bandwidth required is around 82%. If this bit is set, then it is possible to connect two webcams of 1024 bytes x 3 payload per Micro-Frame each. Otherwise, it could be needed to reduce the resolution of the webcams. Note: This bit is used in Host mode operation only. Ignore this bit in Device mode.

Sparse control transaction enable. Some devices are slow in responding to control transfers. Scheduling multiple transactions in one microframe/frame can cause these devices to misbehave. If this bit is set to 0x1, the HC schedules transactions for a control transfer in different microframes/frames.

No Extra Delay Between SOF and the First Packet. Some HS devices misbehave when the host sends a packet immediately after a SOF. However, adding an extra delay between a SOF and the first packet can reduce the USB data rate and performance. This bit is used to control whether the host must wait for 2 us before it sends the first packet after a SOF, or not. This bit can be set to 0x1 to improve the performance if those problematic devices are not a concern in the user host environment.

0 (Val_0x0): Host waits for 2 us after a SOF before it sends the first USB packet.

1 (Val_0x1): Host does not wait after a SOF before it sends the first USB packet.

REF_CLK period. This bit field indicates in terms of nano seconds the period of REF_CLK. The default value of this bit field is set to 0x8 (8 ns/125 MHz). This bit field needs to be updated during power-on initialization, if the GCTL[SOFITPSYNC] or GFLADJ[GFLADJ_REFCLK_LPM_SEL] bit is set to 0x1. The programmable maximum value is 62 ns, and the minimum value is 8 ns. The user should use a reference clock with a period that is an integer multiple, so that ITP can meet the jitter margin of 32 ns. The allowable REF_CLK frequencies whose period is not integer multiples are 16/17/19.2/24/39.7 MHz. This bit field must not be set to 0x0 at any time. If it is not planed to use this feature, this bit field should be set to 0x8 (the default value).